RTL Design

Cadence Design Systems, Inc. is seeking an experienced RTL Design Architect to contribute to the development of next-generation SoCs targeting Hyper-Scalar, Automotive, IoT, and Mil-Aero markets.The ideal candidate will have a strong background in RTL design, with expertise in Verilog and experience with synthesis, SDC creation, and physical design. They...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Solutions (North America) team is looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero markets. Please note, USA-Citizenship...

Job Title: RTL Design Engineer Location: Bay Area, CA OR Austin, TX (Onsite) Mandatory Requirement: Experience in Lint We are looking for RTL Design Engineers with expertise in Lint, CDC, and RDC to join our Static Check team. Ideal candidates will have 5-6 years of experience and at least 2 years working with RTL sign-off tools.Key Qualifications:-...

Position: Memory Controller Designer/RTL EngineerLocation: Austin, TX / San Jose, CA (Hybrid) Type: ContractKey responsibilities include: Drive the timely development and debug of new features on timely development of custom memory controller. Working on SOC IP delivery with all sanity checks. Work on timing debug and closure. Working on LINT, CDC flows and...

Position: Memory Controller Designer/RTL EngineerLocation: Austin, TX / San Jose, CA (Hybrid) Type: ContractKey responsibilities include: Drive the timely development and debug of new features on timely development of custom memory controller. Working on SOC IP delivery with all sanity checks. Work on timing debug and closure. Working on LINT, CDC flows and...

Job Description:Can you provide a JD for a Lint/CDC/RDC – Static check team members – 5-6 Years experienceAt least 2 years’ experience working in RTL sign-off toolsMinimum experience in Lint, CDC, RDC LintsExperience in adding CDC/RDC constraintsExperience in analysis CDC/RDC results and working with design team to disposition the issuesExperience in...

Job Description:Can you provide a JD for a Lint/CDC/RDC – Static check team members – 5-6 Years experienceAt least 2 years’ experience working in RTL sign-off toolsMinimum experience in Lint, CDC, RDC LintsExperience in adding CDC/RDC constraintsExperience in analysis CDC/RDC results and working with design team to disposition the issuesExperience in...

The Self-Driving Hardware team is looking for SOC RTL Designers to work in Austin, TX. SOC RTL designers are expected to understand design requirements, configure and generate interconnect logic, integrate IP blocks with the interconnect, resolve clock, reset, and timing issues, and work with verification, performance, and physical design engineers to bring...

MediaTek Incorporated is a global fabless semiconductor company that enables nearly 2 billion connected devices a year. We are a market leader in developing innovative systems-on-chip (SoC) for mobile device, home entertainment, connectivity and IoT products. MediaTek is the number one Wi-Fi supplier across broadband, retail routers, consumer electronics...

Position: Memory Controller Designer/RTL EngineerLocation: Austin, TX / San Jose, CA (Hybrid) Type: ContractKey responsibilities include: Drive the timely development and debug of new features on timely development of custom memory controller. Working on SOC IP delivery with all sanity checks. Work on timing debug and closure. Working on LINT, CDC flows and...

RTL DesignBay Area, CA OR Austin, TX (Onsite)Contract Expr in Lint/CDC/RDC – Static check team members – 5-6 Years experienceAt least 2 years experience working in RTL sign-off toolsexperience in Lint, CDC, RDC LintsExperience in adding CDC/RDC constraintsExperience in analysis CDC/RDC results and working with design team to disposition the...

RTL DesignBay Area, CA OR Austin, TX (Onsite)Contract Expr in Lint/CDC/RDC – Static check team members – 5-6 Years experienceAt least 2 years experience working in RTL sign-off toolsexperience in Lint, CDC, RDC LintsExperience in adding CDC/RDC constraintsExperience in analysis CDC/RDC results and working with design team to disposition the...

Locations: Bay Area, CA, or Austin, TX (Onsite)Job Description:We are seeking an experienced RTL Design Engineer with 5-6 years of experience to join our Static Check team, specializing in Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis. This role involves RTL sign-off and ensuring design reliability

Locations: Bay Area, CA, or Austin, TX (Onsite)Job Description:We are seeking an experienced RTL Design Engineer with 5-6 years of experience to join our Static Check team, specializing in Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis. This role involves RTL sign-off and ensuring design reliability

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is...

Locations: Bay Area, CA, or Austin, TX (Onsite)Job Description:We are seeking an experienced RTL Design Engineer with 5-6 years of experience to join our Static Check team, specializing in Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis. This role involves RTL sign-off and ensuring design reliability

Title: Physical Design Engineer Duration: Fulltime Location: Austin, TX Description: Develop and own Synopsys RTL-Architect Flow for silicon org Support designers on debug of various flow & tool issues Communicate and work closely with designers and Synopsys on bugs & flow enhancements Perform comprehensive RTL-A based PPA analysis for correlation against...

Title: Physical Design EngineerDuration: FulltimeLocation: Austin, TXDescription:Develop and own Synopsys RTL-Architect Flow for silicon orgSupport designers on debug of various flow & tool issuesCommunicate and work closely with designers and Synopsys on bugs & flow enhancementsPerform comprehensive RTL-A based PPA analysis for correlation against fusion...

Title: Physical Design EngineerDuration: FulltimeLocation: Austin, TXDescription:Develop and own Synopsys RTL-Architect Flow for silicon orgSupport designers on debug of various flow & tool issuesCommunicate and work closely with designers and Synopsys on bugs & flow enhancementsPerform comprehensive RTL-A based PPA analysis for correlation against fusion...

Title: Physical Design EngineerDuration: FulltimeLocation: Austin, TXDescription:Develop and own Synopsys RTL-Architect Flow for silicon orgSupport designers on debug of various flow & tool issuesCommunicate and work closely with designers and Synopsys on bugs & flow enhancementsPerform comprehensive RTL-A based PPA analysis for correlation against fusion...