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Senior CPU RTL Design Engineer

1 month ago

Austin Texas United States MediaTek Full time

MediaTek Incorporated is a global fabless semiconductor company that enables nearly 2 billion connected devices a year. We are a market leader in developing innovative systems-on-chip (SoC) for mobile device, home entertainment, connectivity and IoT products. MediaTek is the number one Wi-Fi supplier across broadband, retail routers, consumer electronics devices and gaming, and its Wi-Fi 6 chipsets are powering the latest networking equipment for faster computing experiences.

Our dedication to innovation has positioned us as a driving market force in several key technology areas, highly including power-efficient mobile technologies, automotive solutions and a broad range of advanced multimedia products such as smartphones, tablets, digital televisions, 5G, Voice Assistant Devices (VAD) and wearables. MediaTek empowers and inspires people to expand their horizons and achieve their goals through smart technology, more easily and efficiently than ever before. We work with the brands you love to make great technology accessible to everyone, and it drives everything we do. Visit www.mediatek.com for more information.


Work Location: Austin, TX


Job Description

The CPU RTL Design Engineer will be responsible for Micro-architecture, RTL coding/integration, Synthesis of complex IP and ARM CPU subsystems. Run RTL quality checks (Lint, Equivalence checks, CDC…) to ensure quality of RTL. Synthesize the design and provide timing constraints to the Physical Design team to ensure RTL meets timing. Work with DV team to define the test plan and verify the RTL thoroughly. Work with WW teams to align on the specification and deliverables.



Minimum Requirements

  • Masters or PHD degree in Computer Engineering or Electrical/Electronic Engineering
  • 8+ Years of experience in RTL design of Complex IP and/or CPU Sub-systems
  • Good understanding of CPU architecture, logic design, synthesis and timing
  • Proficient in RTL Coding in system Verilog
  • Good understanding of RTL quality checks (eg: Lint, CDC, LEC...)
  • Working knowledge in other domains like DV, DFT and PD
  • Strong debugging and scripting skills (Perl, Python, Tcl...)
  • Good communication and general aptitude


Preferred Requirements

  • Prior industry experience in RTL design of IP and/or CPU sub-system