Senior RTL Design Architect
17 hours ago
Cadence Design Systems, Inc. is seeking an experienced RTL Design Architect to contribute to the development of next-generation SoCs targeting Hyper-Scalar, Automotive, IoT, and Mil-Aero markets.
The ideal candidate will have a strong background in RTL design, with expertise in Verilog and experience with synthesis, SDC creation, and physical design. They will also have excellent communication and design management skills, with the ability to work effectively in a multi-disciplinary team.
Responsibilities:
- Design and integrate CPU IP for ARM and/or RISC-V CPU and System IP
- Develop and integrate digital design and IP for Memory and/or Interface IP (PCIe, Ethernet, USB, and other)
- Create detailed micro-architecture specifications and work closely with architects
- Understand performance measurement and refinement, and work with verification/validation teams to create performance verification plans
- Develop and maintain RTL code
- Support verification teams and provide timely specification clarifications and debug support
- Plan and track development schedules to ensure timely IP delivery to all consumers
Qualifications:
- 10+ years of experience in Front End design and/or verification, with a BS/MS in Engineering or Computer Science
- Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
- Expertise in RTL design (Verilog), simulators, and debuggers
- Hands-on experience in synthesis, SDC creation, and physical design
- Experience in C/C++ and/or Python (or scripting language)
- Experience in driving results in multi-disciplinary organizations
Desirable:
- A self-motivated person with good communication and design management skills
- Experience with Cadence front-end toolset
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