Physical Design Engineer

6 days ago


Austin, United States Wipro Full time

Title: Physical Design Engineer

Duration: Fulltime

Location: Austin, TX

Description:

Develop and own Synopsys RTL-Architect Flow for silicon org

Support designers on debug of various flow & tool issues

Communicate and work closely with designers and Synopsys on bugs & flow enhancements

Perform comprehensive RTL-A based PPA analysis for correlation against fusion compiler

Perform timing correlation against against fusion compiler

Investigate PPA inefficiencies and provide feedback to designers

Present the results in a weekly meeting to wider audience

Work closely with physical design team for improved correlation on clock tree, floor plan etc

Minimum Qualifications

RTL2GDSII design flow usage & development in advanced technology nodes (7nm and below)

Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF usage.

Experience in power analysis and reduction using Primetime PX/PrimePower

Experience in timing analysis and convergence using synopsys primetime

Proficiency in scripting languages such as Python and/or Perl is required

Proficiency with TCL is required

Familiarity with low power implementation techniques, clock gating, power gating etc.

Good written and verbal communication skills

Familiarity with memories (SRAM/DRAM/RF/Flop based fifos)

Preferred Qualifications

Power and performance implications with latest technology nodes

Proficiency with version control systems

Experience with rtl power optimization using tools such as Power-Artist

Experience with FSDB analysis for design profiling


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