Senior Design Verification Engineer

1 month ago


San Jose, United States Zenex Partners Full time

Exciting Career Opportunity

Zenex Partners is seeking a talented Design Verification Engineer for a prestigious semiconductor client in the San Jose area

Position: Design Verification Engineer

Location: San Jose, CA (Hybrid: 3-4 days per week)

Pay Range: Up to $120.00/hr W2 Only

Update as of 7/1/24: San Jose market candidates only

About the Role: As a Design Verification Engineer, you will play a crucial role in the functional verification of GPU Subsystems, including Shader, Texture, and Memory Systems. Your expertise in UVM and SystemVerilog will be essential as you develop and refine testbenches, debug RTL models, and ensure high-quality verification processes.

Key Responsibilities:

  • Develop and maintain UVM/SystemVerilog testbenches for unit and cluster-level verification
  • Debug functional errors and triage regression failures
  • Review architecture and micro-architecture specifications
  • Collaborate closely with architects and RTL designers
  • Generate and run test cases, and drive functional/code coverage to closure
  • Integrate C++ reference models into scoreboards

Requirements:

  • 5-15 years of industry experience in design verification
  • Proficient in SystemVerilog/UVM/OVM, and OOP/C++
  • Experience with GPU subsystems (Shader, Texture, Memory Systems) is a plus
  • Strong knowledge of code and functional coverage methodologies
  • Excellent scripting skills in Python or Perl
  • Strong debugging abilities and programming skills
  • Solid understanding of micro-architecture, logic design, and FSMs

If you are passionate about advancing semiconductor technologies and meet the qualifications, we want to hear from you

Apply Now: Send your resume to Kiran@zenexpartners.com or connect with us directly on LinkedIn.

#DesignVerification #UVM #SystemVerilog #SemiconductorJobs #EngineeringJobs #ZenexPartners #SanJose #CareerOpportunity



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