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Principal Design Verification Engineer
3 months ago
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure.
Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable.
Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable.
Discover how we are transforming modern data-driven applications at []).We are seeking experienced Principal Design Verification Engineers with a strong aptitude for working on Emulation Platforms.
Candidates should have a deep understanding of system-level aspects of ASIC development and be skilled in emulation testbench and test plan development.
Responsibilities:
- Develop and execute emulation test benches and test plans.
- Utilize coding and problemsolving skills to contribute to the functional verification of designs.
- Manage the full life cycle of emulation, from planning to systemlevel tests.
- Develop platform agnostic methodologies that scale across traditional DV and emulation and postsilicon bringup for functionality, performance etc.
- Collaborate with software and system validation teams to develop and execute test plans on emulation platforms.
Basic Qualifications:
- Strong academic background in Electrical Engineering (Bachelor's required, Master's preferred).
- Minimum of 8 years' experience in verifying and validating complex SoCs for server, storage, and networking applications.
- Proficiency with industrystandard simulators, revision control systems, and regression systems.
- Professional attitude with the ability to prioritize tasks and work independently with minimal supervision.
- Entrepreneurial, openminded attitude with a customerfocused mindset.
- Authorized to work in the US and available to start immediately.
Required Experience:
- Full verification lifecycle experience on ASICs.
- Proven ability to deploy hybrid techniques, including directed and constrained random testing.
- Experience in stress testing at the system level for bug identification.
- Ability to independently develop test plans and test sequences, generate stimuli, and collaborate with RTL designers to debug failures.
- Skill in identifying and writing test cases using a combination of C and System Verilog constructs to cover functional and code coverage of ASICs.
Preferred Experience:
- Proficiency in scripting tools (Perl/Python) for automating verification infrastructure.
- Experience with System Verilog/UVM/C/C++/SystemC
- Experience with transactors from thirdparty vendors and communication protocols such as PCI-Express (Gen3 and above), Ethernet, DDR4/5, NVMe, etc.
- Familiarity with SystemCbased verification and modeling strategies.
The base salary range for this position is USD 160,000.00 – USD 240,000.00, determined based on location, experience, and comparable employee salaries.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
