Principal Design Verification Engineer

1 week ago

Santa Clara, California, United States d-Matrix Full time
About d-Matrix

d-Matrix is a pioneering company that has revolutionized the field of memory-compute integration with its innovative digital in-memory compute (DIMC) engine. This groundbreaking technology has enabled the company to break through the memory wall, minimizing data movements and paving the way for accelerated AI compute.

With over $154M in funding, including a Series B offering of $110M, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with its chiplets and In-Memory compute approach. The company is on track to deliver its first commercial product in 2024 and is committed to meeting the energy and performance demands of these Large Language Models.

d-Matrix has a diverse team of over 100 employees across Silicon Valley, Sydney, and Bengaluru, with a pedigree that includes companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS, and Wave Computing. The company's past successes include building chips for all the cloud hyperscalers globally, as well as enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, and AT&T.

The Role

We are seeking a highly skilled Principal Design Verification Engineer to join our team. As a key member of our verification team, you will be responsible for leading the design verification cycle from architecture to tape out to bring up. You will work closely with our experienced team to develop and implement verification methodologies, including UVM/OVM, and ensure the successful delivery of our SoC designs.

The ideal candidate will have a strong background in SoC verification, with experience in SystemVerilog, UVM/OVM, and ASIC-SoC Design verification tests and debug. You will be passionate about AI and thrive in a fast-paced and dynamic startup culture. If you are a motivated and experienced verification engineer looking to take on new challenges, we encourage you to apply.

What You Will Bring
  • BS in Electrical Engineering, Computer Science, or related field with 15+ years of industry experience, or MS in Electrical Engineering, Computer Science, or related field with 12+ years of industry experience.
  • Experience in SoC verification cycle from architecture to tape out to bring up.
  • Good knowledge of verification methodologies such as UVM/OVM.
  • Hands-on ASIC-SoC Design verification tests and debug experience.
  • Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
  • Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).
  • Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM).
  • Passionate about AI and thriving in a fast-paced and dynamic startup culture.
  • Experience with C/C++, SystemC (a big plus).
  • Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts.
About Us

d-Matrix is an equal opportunity workplace and affirmative action employer. We are committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

We are proud to be a company that values diversity, equity, and inclusion. We believe that a diverse and inclusive workplace is essential to our success and are committed to creating a culture that is welcoming and empowering for all employees.

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