Memory Firmware Architect

2 months ago

San Jose, United States Droisys Full time

Droisys is an innovation technology company focused on helping companies accelerate their digital initiatives from strategy and planning through execution. We leverage deep technical expertise, Agile methodologies, and data-driven intelligence to modernize systems of engagement and simplify human/tech interaction.


Amazing things happen when we work in environments where everyone feels a true sense of belonging and when candidates have the requisite skills and opportunities to succeed. At Droisys, we invest in our talent and support career growth, and we are always on the lookout for amazing talent who can contribute to our growth by delivering top results for our clients. Join us to challenge yourself and accomplish work that matters.


Client Description


Our client is a major Fortune 500 company and one of the world’s most innovative and cutting-edge technology companies, and this role is in the Interactive department.


Droisys is seeking Memory Firmware Architect job offering Remote or Hybrid Work Options for a long-term job opportunity in Bay Area area of the USA.


Job Title Memory Firmware Architect

Job Location Remote or Hybrid Work

Duration Long Term


The Person:

Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills


The Role:

The Memory IO team is looking for passionate and experienced Firmware designers for the development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP. This opportunity includes enabling new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level.

Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces.


RESPONSIBILITIES:

• Firmware design and development of DDR PHY & DRAM Training steps

• Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power

• Pre-silicon FW coding and simulation against Architectural and RTL models

• Post-silicon lab bring-up and optimization of DDR Init and Run Time FW

• Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin

• Working with SoC/Product firmware teams to define features and specs


Preference & Skill Sets:

• +9 years’ experience as firmware engineer.

• Excellent knowledge of C, C++ and any scripting language ; knowledge of Verilog and Python is a plus

• Ability to adapt learn new toolsets and frameworks is required

• Strong understanding of synchronization techniques (handshakes, message passing) ; knowledge of hardware level clocking and synchronization is a plus

• Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller, or MAC Design experience is preferred

• Strong understanding of computer organization/architecture.

• Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.

• Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)


EDUCATION:

• Bachelor's degree in Electrical or Computer engineering is strongly desired. A Master's or PhD degree is a plus.


Droisys is an equal opportunity employer. We do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. Droisys believes in diversity, inclusion, and belonging, and we are committed to fostering a diverse work environment.

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