Senior Design Engineer
1 month ago
We Are Seeking Senior Design Engineers Who Are Local Or Willing To Relocate To The Santa Clara, CA Area That Have Experience In At Least Once Of The Following
- High Speed Coherent Interconnect
- Serial Interfaces
- PCIe Interface
- High Speed Cache
- CPU Execution Unit
- CPU Fetch Unit
- Memory Subsystems
- Competitive salary and benefits package
- Opportunities for professional development and advancement
- International environment and further career progression
- Getting in touch with bleeding edge technology
- Flexible working hours
- Work-life balance
- Collaborative and supportive work environment
High Speed Coherent Interconnect
" Working with a small team to implement, debug, and verify high-speed chip-to-chip interface
" Building the infrastructure to support bringup and debug in FPGAs and silicon
" Working with the SW team to model and optimize system performance
Serial Interfaces
" We are looking for a skilled design engineers to architect and oversee interfacing our low-speed interfaces to our high-speed interconnect
" These blocks include Boot logic, Serial Interfaces, and debug logic
PCIe Interface
" Working with a small team to implement, debug, and verify a high-performance PCIe interface
" Build the infrastructure to support PCIe during FPGA emulation and bringup
High Speed Cache
" Working on high performance L2 Cache unit serving the needs of state-of-the art AI processing elements
CPU Execution Unit
" Working on Execution Unit
CPU Fetch Unit
" You will be working on state-of-the art Fetch Unit architecture design serving both general purpose as well as AI processing element needs.
Memory Subsystems
" Interface and enhancements of an advanced DRAM control block
What You Need for this Position
Verilog / system Verilog / Synthesis / STA / CDC / LINT
Knowledge of C, Scripting (Perl / Shell / Python / AWK ) is a plus
High Speed Coherent Interconnect
" Experience with shared-memory and NUMA
" Experience with high-speed interconnect
" System performance modelling experience a plus
Serial Interfaces
" Experience with integration and debug of APB, AHB, and AXI interconnects
" Development of internal logic analyzers and profilers
PCIe Interface
" Experience and background with PCIe controller/device design
" Familiarity with bus traffic analyzers and logic analyzers
" Familiarity with data eye and BER analysis
High Speed Cache
" Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi-core designs
" Strong understanding of computer architecture
" Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy
" Logic design experience with state of the art deep submicron technologies specifically low power design techniques
" Knowledge of ARM and x86 and multicore processor designs is a plus
CPU Execution Unit
" Experience with Arithmetic Unit (ALU) logic design with emphasis on high speed processor pipeline designs
" Understanding of processor pipeline designs
" Logic design experience with state of the art deep submicron technologies specifically low power design techniques
CPU Fetch Unit
" Experience with branch prediction algorithms / instruction fetch design of high performance microprocessors
" Strong understanding of computer architecture
" Logic design experience with state of the art deep submicron technologies specifically low power design techniques
Memory Subsystems
" Experience with RS and BCH codes
" Experience with FPGA integration and debug
" Background in design of DRAM interfaces
So if you are a Sr Design Engineer with experience, please apply today
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Caroline Veillon
Email Your Resume In Word To
Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:
caroline.veillon@cybercoders.com
- Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : CV5-1699546L459 -- in the email subject line for your application to be considered.***
Applicants must be authorized to work in the U.S.CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.
This job was first posted by CyberCoders on 08/10/2022 and applications will be accepted on an ongoing basis until the position is filled or closed.
CyberCoders is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. If you need special assistance or an accommodation while seeking employment, please contact a member of our Human Resources team to make arrangements.
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