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Design Engineer
1 week ago
Duties: The ASIC Power Engineer will perform power analysis and optimizations in ASIC for our AR/VR products. Areas of interest include Machine Learning. The primary languages are Python, Tcl, and SystemVerilog.
Responsibilities:
- Perform PPA (Power, Performance, Area) optimization with Fusion compiler.
- Conduct RTL (Register Transfer Level) and netlist level power analysis.
- Execute post-processing and scripting on report log files for format conversion, data analysis, and information extraction.
- Set up, run, debug, and analyze reports of ASIC flows (Synthesis, Physical Design, Power, Timing).
- Implement blocks at RTL and UPF (Unified Power Format).
- Document and communicate findings clearly.
Minimum Qualifications:
- 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.
- Experience with power estimation tools and synthesis, some physical design.
- Knowledge of power trade-offs in design and backend implementation.
- Hands-on experience in scripting and data analysis.
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent experience.
Preferred Qualifications:
- Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules).
- Proficiency in Python and Perl (or similar) scripting and data post-processing tools.
- Proficiency with Excel (or Matlab) for model fitting, data visualization, and analysis.
- Experience in low power design, tools, and methodologies including power intent UPF specifications.
- Experience with silicon power characterization.
- Power profiling experience at the IP/SoC level.
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