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Static Timing Analysis Physical Design
3 months ago
Title : Static Timing Analysis Physical Design
6 Months contract with possibility of extension
Location - San Jose (Hybrid)
Rate - $80 to $120 per hour
Overview: Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.
Responsibilities:
- Strong understanding of digital design concepts, including synthesis, timing analysis, and formal verification.
- Expert in Synopsys timing analysis tool Primetime.
- Experience in timing ecos using Synopsys and other tools.
Functional Activities:
- Perform static timing analysis (STA) and timing optimization, generate and verifies timing constraints, performs SI/Noise analysis, and fixes timing & noise violations at full chip/block level for SoCs.
Technical Skills:
- Familiarity with scripting languages like TCL, Perl, or Python for automation tasks.
- Knowledge of ASIC design flow, including front-end and back-end processes.
Industry Specific Experience:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Ability to collaborate effectively in a team environment and communicate complex technical concepts clearly.
- Understanding of semiconductor fabrication processes and how they influence IC design.
Hybrid Work: This role is Hybrid within the US, with availability required from 8 AM to 5 PM in the candidate's local time zone.
Interview Process:
- Behavioral and situational questions
- Request for case studies or work samples
- Scenario-based questions
- Technical questioning on Physical Design STA Engineer tools and processes
If you are a motivated individual with a passion for creative project management and a drive for excellence, we encourage you to apply. Join our team and contribute to exciting projects in a collaborative and innovative environment.
