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Mixed Signal Verification Engineer
3 months ago
We have exciting opportunities available for both full-time positions and Co-op/internships in CPU and SOC verification, spanning from unit level to chip level.
Responsibilities:
Collaborate closely with architecture and RTL designers to ensure the correctness of design functionality.
Review architecture and design specifications.
Develop comprehensive test plans and environments.
Create tests using assembly, C/C++, SystemVerilog, or vectors based on test plans.
Design coverage monitors and analyze coverage to ensure all test cases are addressed.
Develop checkers in SystemVerilog or C-based transactors.
Write assertions and apply formal verification techniques.
Implement test benches and generate directed/constrained random tests.
Debug failures, run simulations, and track bugs.
Manage schedules and support multi-functional engineering efforts.
Assist in verification flows, automation scripts, and regressions.
Requirements:
Deep understanding of digital logic design, CPU/SOC architecture, and microarchitecture.
Proficiency in SystemVerilog.
Experience with C/C++.
Familiarity with verification methodologies and tools such as simulators, waveform viewers, and coverage collection.
Basic understanding of formal verification methodology is advantageous.
Strong skills in Python, TCL, or other scripting languages is a plus.
Excellent problem-solving abilities.
Strong written and verbal communication skills.
Highly organized and self-motivated.
Ability to thrive in a team environment and meet aggressive deadlines.
Education and Experience:
PhD, Master's Degree, or Bachelor's Degree in a technical subject area.
Apply now as interviews are being scheduled
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