asic rtl design engineer

Duration: 12 Months (Chances for extension) THE ROLE: In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. THE...

REMOTE OFFSITE:  FROM HOME2 Contract positions interviewing now, for Mid November start dates:12-18 Months + CONTRACTSENIOR ASIC RTL Design (need ASIC-RTL Design not FPGA)Strong VerilogHigh Speed Memory Interface ExperienceAXI busMulticlock Domain DesignsLogic synthesis & Timing constraintsForward Error Correction (FEC), Bit Rate Error (BER)...

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. THE PERSON: You are passionate about digital design, power...

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. Global company...

Duration: 12 Months (Chances for extension) THE ROLE: In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. THE...

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements. THE PERSON: You are passionate about digital design, power...

Job DescriptionJob DescriptionJOB DUTIES:You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, Client/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP. You will work closely with analog circuit designers,...

ASIC RTL Design Engineer - Memory PHYBoxborough, MA (Hybrid)12 + MonthsMust have strong ASIC/Digital Design, RTL Coding (Verilog/SystemVerilog), C/C++, Synthesis, Timing Closure, and CDC experience.Plus:DDR/LPDDR, Memory PHY, high-speed interface design, and Python/TCL scripting.Dexian stands at the forefront of Talent + Technology solutions with a presence...

Lancesoft is seeking a digital design engineer in Santa Clara, CA, to drive low-power design strategies for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area, ensuring reliable silicon meeting product requirements.You will work with RTL, physical design, and verification teams across time zones,...

THE ROLE:In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.THE PERSON:You are passionate about digital design,...

ASIC/RTL Design Engineer 5 - 2 - San JoseExperience - 10+ Years preferableJOB DUTIES: You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP.You will...

Cerebras Systems is seeking a Senior Front-End Design Engineer to lead RTL design for the Wafer Scale Engine. You will work with design verification, physical design, software and system teams to deliver high-performance, power-efficient chip implementations from concept to production. The role requires a Master’s degree in CS/EE and 8+ years of experience...

TekWissen Group leads global staffing and supports a major American semiconductor client in Santa Clara, CA. The role focuses on driving low-power strategies, synthesis, and timing closure for complex SoC/IP designs. Collaboration with RTL, physical, and verification teams ensures robust PPA and reliable silicon for advanced nodes. The ideal candidate excels...

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking...

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking...

Cerebras Systems is seeking a Senior Front-End Design Engineer to lead RTL design for the Wafer Scale Engine. You will work with design verification, physical design, software and system teams to deliver high-performance, power-efficient chip implementations from concept to production.The role requires a Master’s degree in CS/EE and 8+ years of experience...

TekWissen Group leads global staffing and supports a major American semiconductor client in Santa Clara, CA. The role focuses on driving low-power strategies, synthesis, and timing closure for complex SoC/IP designs.Collaboration with RTL, physical, and verification teams ensures robust PPA and reliable silicon for advanced nodes. The ideal candidate excels...

Cisco Systems, Inc. is seeking an experienced IC design professional to lead DFT RTL development and verification for cutting-edge silicon platforms.You will collaborate with frontend RTL and backend physical design teams to ensure robust, high-performance designs that align with Cisco Silicon One architecture and strategic objectives. The role emphasizes...

ResponsibilitiesLead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designsIntegrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibilityThoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA)...

United States Digital Space LLC is seeking a Senior RTL Design Engineer to develop next-generation ASICs for space and ground infrastructure. You will define micro-architecture, implement RTL in Verilog/SystemVerilog, and collaborate with verification to ensure fully verified designs for silicon bring-up.The role requires 5+ years in RTL implementation,...