IC Layout Engineer

7 hours ago

Cedar Rapids, Iowa, United States Skyworks Full time

About Skyworks

Skyworks is a leading innovator of high-performance analog semiconductors, powering the wireless networking revolution. Our broad technology expertise and extensive product portfolio enable us to Connect Everyone and Everything, All the Time.

Our Culture

We value open communication, mutual trust, and respect. Our fast-paced environment fosters global collaboration, minimal layers of management, and the freedom to make meaningful contributions. We encourage creative thinking and are excited about the opportunity to work with talented individuals who are changing the way the world communicates.

Job Summary

We are seeking a highly motivated Layout Summer Intern to support the layout of Analog integrated circuits, utilizing commercial/standard bulk CMOS and SOI technologies in accordance with design rules. The successful candidate will work closely with the layout team and manager to support design engineers in the layout and verification of analog and integrated circuits for wireless consumer electronic products using the Cadence Design environment and Calibre verification tools.

Key Responsibilities

  • Support the layout team in the design and verification of analog and integrated circuits.
  • Collaborate with design engineers to ensure accurate and efficient layout and verification processes.
  • Utilize Cadence Virtuoso and Calibre tools to perform layout vs schematic (LVS) and design rule checks.
  • Develop and maintain a strong understanding of semiconductor processes and structures, including CMOS FETs, capacitors, and resistors.
  • Participate in the development and implementation of new design methodologies and tools.
  • Contribute to the improvement of the layout and verification process through continuous learning and improvement.

Requirements

  • Currently enrolled in a layout of integrated circuits program at an accredited college or technical institution.
  • Classroom experience in the layout of bulk CMOS blocks.
  • Able to plan the placement of circuit components in an overall physical design.
  • Basic understanding of semiconductor processes and structures, including CMOS FETs, capacitors, and resistors.
  • Entry-level knowledge to perform LVS and DRC using Calibre or Cadence verification tool.
  • Basic experience and competency in using Cadence Virtuoso and Calibre tools.
  • Good communication skills, both verbal and written.
  • A self-starter and team player with the ability to learn on the job.

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