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Senior IC Packaging Specialist

2 months ago

San Jose, California, United States Broadcom Corporation Full time
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Position Overview:

Role Summary
  • Collaborate with the chip design team and Analog/Digital IP/Phy stakeholders to optimize chip floorplan and bump patterns for packaging design needs.
  • Engage with marketing and IC design teams to determine the best packaging solutions based on cost, performance, manufacturability, and reliability.
  • Partner with IC design, system design, and thermal engineering teams to create custom packaging solutions utilizing Cadence APD.
  • Ensure that the developed packages comply with signal integrity, power integrity, thermal, and mechanical specifications.
  • Define and select the package Bill of Materials (BOM) in collaboration with OSAT partners.
  • Oversee the IC packaging process from initial concept through development, qualification, and mass production.
  • Generate comprehensive package design documentation and assembly guidelines.
  • Coordinate with packaging assembly and substrate suppliers for new product introductions, qualifications, and production scaling.
  • Work alongside various operational groups such as product engineering, foundry, testing, and quality assurance.
  • Engage with tier-one external clients as necessary to assist with quality and other issue resolutions.
  • Support new product introduction (NPI) activities, package reliability assessments, and multi-sourcing strategies for manufacturing flexibility.
  • Collaborate closely with quality assurance teams to address and resolve quality concerns.
Qualifications:
  • Education: Degree in Electrical Engineering or Mechanical Engineering.
  • Experience: Bachelor's degree with 8 years, Master's degree with 6 years, or PhD with 3 years of relevant experience.
  • Comprehensive understanding of signal integrity and power integrity concepts, including characteristic impedance and s-parameters.
  • Proficient in Cadence APD for custom substrate design.
  • Hands-on experience with advanced assembly techniques for flip-chip, wirebond, and multi-chip module (MCM) packages.
  • Solid understanding of materials related to Chip Packaging Interaction (CPI).
  • Familiarity with wafer back-end-of-line processes relevant to CPI.
  • Knowledge of advanced substrate manufacturing processes.
  • In-depth expertise in failure analysis methods for advanced silicon products.
  • Conceptual understanding of package cost structures.
  • Strong project management, communication, and leadership capabilities.
  • Familiarity with GD&T and the ability to interpret mechanical drawings.
  • Solid grasp of manufacturing and quality engineering principles.
Candidates should be prepared to expand their expertise across multiple disciplines, including manufacturing, quality, materials, electrical, thermal, and mechanical engineering.

Compensation and Benefits Overview:

The annual base salary range for this role is competitive and commensurate with experience.

This position is also eligible for a discretionary annual bonus and equity participation as per relevant plan documents.

Broadcom offers a comprehensive benefits package, including medical, dental, and vision coverage, 401(K) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), paid holidays, sick leave, and vacation time. The company adheres to all applicable laws regarding Paid Family Leave and other leave policies.

Broadcom is an equal opportunity employer, considering qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by law.

Note: If you are located outside the USA, please ensure to provide a home address for future correspondence.