Senior Verification Expert

1 month ago


San Jose, California, United States CV Library Full time

Job Overview

This Senior Verification Engineer position is an excellent opportunity to utilize your expertise in verification closure, SoC debug, and PCIe design.

About the Role

We are seeking a highly skilled Senior Design Verification Engineer with strong knowledge of System Verilog HVL, C/C++, and SV/UVM. The ideal candidate will have experience in porting/testing FPGA & Emulation (Zebu) Hardware realization Platform and can work on complex SoC debug and PCIe design.

Responsibilities

  • Liaise with team members to achieve verification closure.
  • Utilize skills in Make/Perl/Python programming languages.
  • Evaluate customer satisfaction through effective reporting.
  • Collaborate with cross-functional teams to develop comprehensive test plans, BFM/Driver/Monitor/Scoreboard components, and ensure gate level simulations, assertions, and coverage closure.

Requirements

  • Minimum 10 years of experience in System Verilog HVL, C/C++.
  • At least 8+ years of experience in Senior Design Verification Engineer roles.
  • Strong understanding of Complex SoC Debug and PCIe Expertise.

Benefits

  1. Competitive compensation package including $150,500-$185,000 annual salary.
  2. Extensive benefits such as Medical, Dental, Vision Insurance.
  3. Paid Time Off and Tuition Reimbursement opportunities.
  4. Comprehensive Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options.

About eInfochips

eInfochips, an Arrow company, is a leading provider of product engineering and semiconductor design services with over two decades of history and 40M deployments in 140 countries.

Contact Information

Please note that this job posting is for information purposes only.



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