Senior Principal DFT Test Engineer

2 days ago


Austin, Texas, United States NXP Semiconductors Full time
About the Role

NXP Semiconductors' Automotive Embedded Systems business line is seeking a highly skilled Senior Principal DFT Test Engineer to join our team. As a key member of our product and test engineering group, you will be responsible for supporting new cutting-edge automotive microprocessor products and collaborating with global and cross-functional teams to improve DFT processes, methodologies, standards, and quality.

Key Responsibilities
  • Lead the development of DFT post-Si solutions for automotive products, working closely with DFT, Verification, Front-End, Physical Design, FA, and Product and Test engineering teams.
  • Collaborate with cross-functional teams to define new methodologies, processes, and standards with a focus on quality and productivity.
  • Improve scan diagnostics and Failure Analysis flows, working closely with DFT Design & DFT Design Quality teams.
  • Enhance scan test program flows, including binning/scan logging for both Wafer Sort and Final Test programs.
  • Be involved in NPIs from definition to production launch, ensuring seamless integration of DFT solutions.
  • Resolve DFT-related issues between PETE and DFT teams on NPIs.
  • Assist test engineering with 1st silicon bring-up in regards to DFT.
  • Drive innovative solutions to improve testability and cost in our designs.
  • Define characterization and production scan flow standards.
  • Support post-silicon activities, working with DFT, test engineering, product engineering, FA, and validation teams.
Requirements
  • BS/MS in Electrical/Electronics Engineering.
  • Thorough understanding of ATE architecture, DFT Tester Pattern generation/conversion, Test Program flow development.
  • Senior SoC DFT engineer with experience in all aspects of DFT, including scan & ATPG, memory BIST, logic BIST, analog test, and post-silicon support.
  • 10+ years of hands-on experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG.
  • Strong expertise in DFT architectures, methodologies, and techniques, including scan insertion, ATPG algorithms, BIST Architectures, and JTAG on SOC devices.
  • Experience with Siemens Tessent ATPG tools preferred.
  • Experience with Siemen's Scan Streaming Network (SSN) highly desirable.
  • Good understanding of design flow from specification / micro-architecture definition to design and verification, timing analysis, and physical design.
  • Familiarity with industry standards such as IEEE JTAG and IEEE 1687 (IJTAG).
  • Scan Diagnostics experience highly desirable.
  • Automated Test Equipment (ATE) knowledge and experience a plus.
  • Identify new opportunities to innovate and improve quality and productivity in DFT and Product and Test community.
  • Good team player with ability to work across functional teams, sites, and cultures in issues resolution.
  • Demonstrate good analysis and problem-solving skills.
  • Self-motivated. Excellent written and verbal communication skill.
Location
  • Austin, TX.


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