ASIC Design Engineer
1 week ago
Apple is seeking a highly skilled ASIC Design Engineer to join our team and contribute to the development of our high-bandwidth multi-client memory subsystems. As a key member of our team, you will work on crafting special purpose cache and controller designs that are part of the SOC memory hierarchy.
Key Responsibilities- Participate in cache micro-architecture development from specifications found from architecture guidelines and model analysis.
- Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team.
- Develop and debug RTL design of different sections of the cache.
- Work with physical design team to close timing of the cache.
- Development of memory systems.
- Experience in RTL/micro-architecture definition.
- Experience in PPA (performance/power/area) analysis.
- Knowledge of dedicated coherent memory system or interconnect architectures.
- Strong cache design background including good understanding of different memory organizations and trade-offs.
- Knowledge of dedicated memory subsystem and DRAM controller.
- Hands-on experience with multi-processor cache coherence protocols.
Bachelor's Degree + 10 years of experience.
Apple is an Equal Opportunity EmployerWe are committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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