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Senior Physical Design Engineer
2 months ago
We are seeking a highly skilled Senior Physical Design Engineer to join our team at Esperanto-USA. As a key member of our engineering team, you will be responsible for designing and developing complex ASICs and SOCs using advanced process technology nodes.
Key Responsibilities:- Design and develop SOC blocks from RTL to clean GDS, collaborating with other PD engineers to drive blocks to signoff closure.
- Work on multi-voltage and multi-clock domain designs, utilizing low power UPF flow and advanced EDA tools.
- Debug constraints, perform physical-aware synthesis, and optimize low power using mmmc.
- Synthesize clock trees, ensuring stringent skew and insertion delay targets, and perform signal integrity-aware routing.
- Run through blocks STA closure, probe reports, and collaborate with RTL designers to achieve timing closure and best PPA.
- Experience with full chip integration, full chip planning, power grid, bumps AP routing, full chip timing closure, EMIR, physical verification, and packaging support is desirable.
- 10+ years of ASIC Physical Design experience, with successful tapeouts at the latest technology nodes (7nm experience preferred).
- Strong interpersonal and collaboration skills, with experience working in a fast-paced startup culture.
- Proficiency with EDA tools, including FC, DC, ICC2, StarRC, Primetime, ICV, Redhawk, mPower, and scripting languages like TCL and Perl.
- Experience with UPF and low-power multi-voltage designs, as well as full product life cycle from 1st Tapeout to metal spins to full silicon production.
- Base salary range: $100,000 - $300,000.
- Eligibility for stock options and benefits.
