Senior Chip Packaging Design Engineer

3 weeks ago


Mountain View, California, United States Saxon Global Full time
Job Title: Senior Chip Packaging Design Engineer

Job Summary:
We are seeking a highly skilled Senior Chip Packaging Design Engineer to join our team at Saxon Global. As a key member of our packaging design team, you will be responsible for designing and developing high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.

Key Responsibilities:
  • Design and develop high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools.
  • Create die and BGA symbols from scratch or from spreadsheet inputs.
  • Set up design environment, including tech files, stack ups, and constraints.
  • Set up Constraint Manager from scratch for complex packages.
  • Routing signals and matching length both manually and using tool features.
  • Design file management and documentation from initiation to final signoff.
  • Generation of POD.
  • Solid knowledge of top package suppliers design rules and basic manufacturing practices.

Desired Qualifications:
  • Experience with Cadence Orbit I/O.
  • 2.5D interposer design layout experience using Cadence SiP.
  • Experience with Virtuoso and/or Innovus for 2.5D interposer design.
  • Experience with Synopsys tools for 2.5D interposer design.
  • Experience writing and implementing custom scripts in Cadence tools.
  • Familiar with Cadence PVS.

About Saxon Global:
Saxon Global is a leading provider of global workforce solutions. We are committed to delivering exceptional service and value to our clients and candidates. If you are a motivated and experienced Senior Chip Packaging Design Engineer looking for a new challenge, please submit your application today.

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