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Design Verification Specialist

2 months ago

Sunnyvale, California, United States Programmers Full time
Design Verification Services

We offer comprehensive verification of designs using advanced methodologies to ensure robust testing and efficient testing processes.

Key Responsibilities:

  • Creation of testbenches using System Verilog Universal Methodology (UVM), Python, and C, tailored for various testing scenarios.
  • Development and integration of C tests, APIs, and software build flows to ensure robust testing.
  • Seamless integration of UVM testbenches for efficient testing processes.
  • Developing and debugging tests for functionality, power, performance, error handling, and connectivity, applicable to both RTL and Gate Level Netlist designs.
  • Setup and debugging of continuous integration and regression testing for simulations at RTL and Gate Level Netlist.
  • Utilization of Unified Power Format (UPF) for power-aware simulation and emulation.
  • Creation and maintenance of XProp simulations and testbenches.
  • Collection and closure of coverage, along with thorough documentation of tests, testbenches, use cases, exclusions, and status updates.

Benefits:

  • Power-Aware Simulation
  • Continuous Integration & Regression Testing
  • Test Development and Debugging