Senior Mixed-Signal Design Engineer
1 month ago
At Infinera, we are seeking a highly skilled Mixed-Signal Design Engineer to lead the design efforts of high-speed low-noise clocking circuitry, including fractional-N phase locked loops and clock distribution networks.
Key Responsibilities:- Design, simulate, and verify high-frequency fractional-N PLLs.
- Architect, model, and simulate noise accumulation and skew of clock distribution trees.
- Model, optimize, and measure phase noise and jitter performance, and skew of entire clocking networks.
- Design and implement high-frequency / low-noise VCOs.
- Collaborate and/or supervise other team members for system design implementation, layout floor planning, and system level modeling.
- Experience in designing low phase noise LC-VCO based PLLs to production.
- Knowledge in design trade-offs among different VCO topologies for MM-Wave applications.
- Hands-on experience in designing clock distribution networks in Cadence environment.
- Ability to model phase noise and spurs of frac-N PLLs.
- Extensive experience in designing and implementing high frequency VCOs and clock trees with EMX tools.
- Understanding in CMOS analog / mixed signal design overall.
- Ability to supervise testing activities.
- Fluency in verbal and written communications.
- Ability to independently resolve issues and conquer design challenges.
- Self-motivation and attention to detail.
- Good interpersonal skills.
- M.S. or Ph.D. in Electrical Engineering.
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law.
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