Senior CPU Subsystem Design Engineer

2 weeks ago

San Jose, California, United States Intel Full time
Job Details:

Job Description:

As part of Intel's Programmable Solutions Group (PSG), we are seeking a highly skilled Senior CPU Subsystem Design Engineer to join our team. In this role, you will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrating logic of IP blocks and subsystems into a full chip SoC or discrete component design.

You will participate in the definition of architecture and microarchitecture features of the block being designed, perform quality checks in various logic design aspects ranging from RTL to timing/power convergence, and apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

You will also review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features, follow secure development practices to address the security threat model and security objects within the design, and work with IP providers to integrate and validate IPs at the SoC level.

Additionally, you will work with Physical Design teams to synthesize their RTL block and provide estimates of timing, area, and power.


Qualifications:
  • Bachelor's degree in computer engineering, electrical engineering, or related field.
  • 10+ years of relevant experience in CPU based SoC designs, processor based SoC architectures, NoC design and integration with AMBA interconnect protocols, RTL development using ASIC development techniques and designs flows at modern technology nodes, and experience with scripting languages (e.g., Python or Perl).
  • Experience with digital design involving multiple clock domains and clock, power management, low power design, tools, and methodologies, and power intent UPF specifications.
  • Experience with Ethernet, PCIe, or TSN.

Preferred Requirements:
  • Master's degree in computer engineering, electrical engineering, or related field.
  • 6+ years of experience in digital design involving multiple clock domains and clock, power management, low power design, tools, and methodologies, and power intent UPF specifications.

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, San Jose

Business group:
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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