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Senior RTL Design Engineer

2 months ago

Chandler, Arizona, United States ACL Digital Full time
Job Summary

We are seeking a highly skilled Senior RTL Design Engineer to join our team at ACL Digital. As a key member of our design team, you will be responsible for developing high-speed digital designs, with a focus on Ethernet IP development.

Key Responsibilities
  • Design and develop complex digital circuits, including Ethernet MAC and PCS development
  • Integrate 3rd party Ethernet MACSec and IPSEC into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register maps
  • Develop Block Level Constraints and run synthesis
  • Perform Static Timing Analysis of the MACSec digital logic and review post-layout timing
  • Support Verification and Validation groups in testing of the IP blocks and other similar logic blocks
  • Integrate and simulate memory controller designs, including integration into processor sub-systems and IP used in the FPGA fabric of the device
  • Provide ongoing customer support to ensure the IP cores are robust with performance that meets the customer performance and/or power goals
  • Support RTL design engineers with less experience for the functions shown above
Requirements
  • Minimum of 10 years of proven silicon design experience in high-speed RTL design, Ethernet, and other related logic
  • Strong experience in RTL design, design verification, synthesis & formality, Static Timing Analysis, and Verilog simulation tools
  • Ability to design complex state machines & data path logic, write detailed design specifications, and communicate effectively with team members
  • Bachelor's/Master's in electrical engineering, Computer Engineering or Computer Science
Preferred Qualifications
  • FPGA and ASIC System On Chip Design Experience
  • Lab Experience for System Level Validation