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Senior RTL Microarchitecture Engineer

2 months ago

California, United States DAC Search Inc Full time

Company Overview: DAC Search Inc, led by Richard Goldstein, is dedicated to providing specialized recruiting services for the Semiconductor, EDA, and AI Chip sectors, focusing primarily on innovative startups.

About Our Client: Our client is at the forefront of developing foundational technologies for chiplet-based semiconductor design. As an early-stage startup, they are pioneering advancements in the multi-chiplet system-on-package paradigm. Their mission is to drive the next wave of growth in the semiconductor industry, and they are seeking passionate professionals to join their seasoned and dynamic team. The founding members previously established a successful startup that was acquired by a major player in the industry, lending them significant credibility. The executive and board teams are exceptionally strong.

Position Overview: We are looking for a skilled RTL Microarchitect who thrives in startup environments and embraces the dynamic nature of such roles.

Location: This position requires on-site presence in either Santa Clara, CA or Bengaluru, India. The small team values daily in-person collaboration.

Key Responsibilities:

  • Design and develop microarchitectures for a variety of highly configurable IPs.
  • Implement microarchitecture and RTL coding to ensure optimal performance, power efficiency, and area utilization.
  • Collaborate with software teams to define configuration requirements and verification collateral.
  • Engage with verification teams on assertions, test plans, debugging, and coverage.

Qualifications and Preferred Skills:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • A minimum of 8 years of hands-on experience in microarchitecture and RTL development.
  • Proficiency in Verilog and System Verilog.
  • Familiarity with industry-standard EDA tools and methodologies.
  • Experience with large, high-speed, pipelined, stateful designs, and low-power designs.
  • In-depth knowledge of on-chip interconnects and NoCs.
  • Experience with ARM ACE/CHI or similar coherency protocols.
  • Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs.
  • Familiarity with RAS designs, QoS in fabrics, and PCIe/IO is advantageous.
  • Experience with modern programming languages such as Python is a plus.
  • Exceptional problem-solving skills and meticulous attention to detail.
  • Strong communication and collaboration abilities.

Application Process: Interested candidates are encouraged to apply through the appropriate channels.