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SoC Physical Design Engineer, STA/Timing Expert
1 month ago
As a SoC Physical Design Engineer, you will be responsible for the physical implementation of design partitions for highly complex SoCs using state-of-the-art process technology.
Key Responsibilities- Collaborate with design teams to understand and debug constraints, facilitating logic changes to improve timing.
- Work with the Physical Design team to highlight issues and best practices.
- Create timing ECOs for project tapeout.
- Develop and maintain scripts and methodologies for analysis and runs.
- Generate documentation and contribute to guidelines/specs.
- Analyze timing paths to identify key issues.
- Implement timing infrastructure.
- Minimum BS and 3+ years of relevant industry experience.
- Hands-on experience in STA.
- Familiarity with timing aspects of large high-performance SoC designs in sub-micron technologies.
- Proficiency in STA and methodologies for timing closure, with a fundamental understanding of noise, crosstalk, and OCV effects.
- Familiarity with circuit modeling, including SPICE models and worst-case corner selection.
- Good programming skills with Perl and TCL.
- Experience with large design STA and Timing Closure.
- Familiarity with ECO techniques and implementation.
- Excellent communication skills to accurately describe issues and follow them through to completion.
At Apple, we offer a comprehensive compensation package, including base pay, discretionary bonuses, and commission payments. You will also receive benefits such as comprehensive medical and dental coverage, retirement benefits, and a range of discounted products and free services.
