Senior Physical Design Engineer

3 weeks ago


San Jose, California, United States TSMC Full time

Job Summary

We are seeking a highly skilled Physical Design Engineer to join our team at TSMC. As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS, including floorplan, place and route, CTS, STA, PDV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC blocks.

Responsibilities

  • Complete entire physical implementation of the block level and tapeout production chip
  • Block level floorplan with the ability to analyze the quality of the floorplan
  • Customized Clock tree structure and Place & Route
  • Implement ECOs for timing closure
  • Signal EM/Noise and Power IR/EM analysis and fix
  • DRC/LVS/ERC/ANTENNA analysis and clean up
  • Physical verification sign off

Requirements

  • Master's degree in Electrical/Computer Science Engineering with 12+ years of industry experience, or Bachelor's degree in Electrical/Computer Science Engineering plus 18+ years of industry experience
  • Netlist (or RTL)-GDS physical implementation experience
  • In depth knowledge of major EDA tools/design flows
  • Experience with TSMC N16 or below technology
  • Experience in block level implementation or chip integration and signoff
  • Experience in Perl/TCL language programming

About TSMC

TSMC is a leading semiconductor foundry company that provides a wide range of semiconductor manufacturing services to customers around the world. We are committed to delivering high-quality products and services to our customers, and we are looking for talented individuals to join our team.



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