Principal Engineer in Power Assessment

2 weeks ago

Jackson, Mississippi, United States Entertainment Services Alliance, Inc. Full time

Job Overview:
Are you eager to influence the future of semiconductor design? At Entertainment Services Alliance, Inc., we present an exceptional opportunity for a seasoned Power Optimization Engineer to become part of our successful team in a vibrant and diverse environment.


We are assembling a team dedicated to developing top-tier silicon platforms leveraging our proprietary IP Compute Subsystem solutions, targeting sectors such as high-end mobile, infrastructure, and automotive.

Our goal is to showcase effective performance by architecting, designing, implementing, and fabricating innovative silicon test chips utilizing the latest SoC process nodes and packaging technologies.


This initiative is both exciting and unique, as we are pioneering how the next generation of leading computing devices are constructed across the industry.

Join us to contribute to the solution.

Responsibilities:


You will be part of a focused team where we assess and enhance the power efficiency of our next-generation computing solutions through innovative technologies, methodologies, and tools.

Evaluate the power efficiency of SoC design features from initial estimation to final product validation.

Develop and execute RTL simulator and emulator-based workloads to assess the power consumption of the hardware design.


Conduct pre-silicon design power measurements throughout the SoC development lifecycle, from early modeling and RTL analysis to detailed timing-annotated netlist analysis.


Power analysis engineers collaborate with various teams, including SoC Architecture, Performance Analysis, Microarchitecture Design, and Physical Design, to develop and analyze real software use cases alongside the physical hardware.

Establish relevant metrics and visualizations to illustrate the hardware power signature and capabilities of the compute subsystems.

Review the quality and accuracy of data generated by the latest EDA power analysis tool flows.

Continuously innovate by enhancing the power analysis methodologies employed by the team.

Required Skills and Experience:
We are looking for experienced engineers for a multi-disciplinary role in power analysis.

Ideal candidates possess prior experience in power analysis or are motivated engineers with valuable transferable skills from design, implementation, or verification backgrounds.

Proficient in executing power modeling or pre-silicon power analysis flows.

Experience with low power design features and techniques, including clock and power gating, voltage/frequency scaling, and memory/logic retention.

Ability to comprehend and balance trade-offs between power, performance, and area.

Familiarity with developing RTL using Verilog, System Verilog, or VHDL.

Knowledge of the Physical Implementation flow from RTL through Synthesis, Place & Route to STA.

Preferred Skills and Experience:

A background in development based on Arm processor-based SoC system designs.

A Bachelor's (BS), Master's (MS/MSc), or equivalent degree in Electronics, Electrical, or Computer Engineering. Candidates with other degrees will be considered if they have relevant work experience.

Development or analysis of CPU or Graphics benchmarks for PPA analysis.

Experience using tools for power analysis, power delivery, and signoff (e.g., PowerPro, PrimePower, Redhawk, etc.).

Background in running simulation/emulation tools (e.g., VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc.).


Good understanding of the concepts and tools related to synthesis, place & route, clock tree synthesis, constraint development, and timing closure (e.g., Innovus, Tempus, etc.).

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