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Design Verification Specialist

2 months ago

San Jose, California, United States Women Impact Tech Full time
Job Title: Design Verification Engineer

We are seeking a highly skilled Design Verification Engineer to join our team at Women Impact Tech. As a key member of our verification team, you will play a critical role in ensuring the quality and reliability of our GPU Subsystems.

Responsibilities:
  • Triage and resolve regression failures in our testbench
  • Debug functional errors in our RTL model using simulation and debug tools
  • Maintain efficient and clean regression status
  • Develop scalable SystemVerilog/UVM testbenches for unit level and/or cluster level verification
  • Review architecture and micro-architecture specifications
  • Closely collaborate with architects and RTL designers
  • Define, maintain, and execute unit level and/or cluster level verification test plans
  • Generate and run test cases on logic simulation models
  • Code functional coverage models and SystemVerilog assertions
  • Drive functional coverage and code coverage to closure
  • Integrate C++ reference model into scoreboards
Requirements:
  • 5-15 years of industry experience in a design verification role
  • Proficient in SystemVerilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology
  • Experience in creating, running, and debugging of SystemVerilog/UVM constraint-random testbench
  • Excellent working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines
  • Strong functional verification experience including test planning, testbench architecture, test/coverage model/assertion development
  • Strong debugging skills
  • Strong programming skills with good understanding of algorithms and data structures
  • Good verbal and written communication skills