Senior ASIC Verification Engineer
3 days ago
At Recogni, we're pushing the boundaries of artificial intelligence (AI) to transform the world. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for various markets. We're a well-funded, fast-paced startup company with headquarters in both San Jose, CA, and Munich, Germany, and a talented team of remote workers. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.
About the Role:
We're seeking a senior ASIC verification engineer to join our team. As a senior member of our ASIC team, you'll be responsible for the pre-silicon correctness and quality of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of our flagship perception module product for autonomous driving applications. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power. Your responsibilities will be wide-ranging and include working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular System Verilog and UVM, handling bug tracking and coverage convergence, and developing scripts and methodologies for the front-end ASIC flow.
Responsibilities:
Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks. Develop the block-level, sub-system, and full-chip verification environment and tests to implement test plans. Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances. Triage and debug functional and performance issues with the design-under-test. Handle bug tracking and coverage convergence. Perform diagnostic and post-silicon validation tests in the lab.
Required Qualifications:
5+ years of ASIC verification experience. Knowledge of ARM/MIPS/RISC-V Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation. Familiarity with AMBA/APB/AXI Protocol. Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C .... Excellent Verilog/System Verilog programming skills. Experience with UVM (or similar). Deep understanding of object-oriented programming principles, constrained random stimulus, and a coverage-driven verification approach. Scripting experience (Python, Perl, TCL, shell programming) highly desirable. Interest to explore AI architectures for convolution, transformer, and other kinds of workloads. Self-starter and highly motivated to work in a dynamic start-up environment. B.S. degree in Electrical or Computer engineering (or similar field).
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