3D Semiconductor Packaging Solutions Architect
4 weeks ago
A key role is available for a technologist to architect 3D semiconductor packaging solutions and heterogeneous integration processes. The ideal candidate will work across the industry to identify partners, tools, and technologies to develop advanced packaging solutions for 3D-ICs, 2.5D, chiplets, silicon interposers, and other applications utilizing high density interconnect such as wafer-to-wafer and die-to-wafer stacking.
Key Responsibilities:
• Lead technical teams to develop 3D heterogeneous packaging solutions such as fine pitch electrical interconnects, die-to-wafer, and wafer-to-wafer stacking.
• Evaluate technology integration strategies, process and metrology tools, and IP technology transfers.
• Lead intra and inter technology transfer for advanced packaging including process documentation, process engineering, and process calibration.
• Represent the organization as the prime technical contact on contracts and projects, interacting with senior external personnel on significant technical matters.
• Develop collaborative relationships with Engineering Managers and Program Leadership to support business demands, including bid and proposal.
Requirements:
• Bachelor's Degree and a minimum of 9 years of prior relevant experience, or Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.
• Ability to obtain a US government Top Secret SCI Security Clearance.
• Experience in advanced semiconductor packaging technology development from R&D to Development and into Production.
• Experience in BEOL processes, including ASML i-line photolithography, microbumping, TSV plating, CMP, etc.
Preferred Skills:
• Experience with IP licensing and technology transfer.
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