Wireless Silicon Design and Optimization Specialist
3 days ago
At Apple, our wireless silicon development team is responsible for designing and implementing highly energy-efficient wireless SoCs. We're looking for a talented FE Design and Timing Analysis Engineer to join our team. This role involves working with cross-functional groups to design and optimize our wireless SoCs from RTL to delivery of our final GDSII.
Estimated Salary: $226,000 - $401,300
About the Role
The successful candidate will be involved in all phases of implementing high-performance, low-power wireless SoCs. Responsibilities include generating chip or block level static timing constraints, synthesizing design with UPF/DFT/BIST, closing timing on critical blocks by working with design and PD teams, performing timing optimization and implementing the design for functionality, generating and implementing functional ECOs, running static timing analysis flows at chip/block level and providing guidelines to fix violations to other designers, and participating in establishing/improving CAD and design flow methodologies.
Key Qualifications
To be successful in this role, you'll need a Bachelor's degree and 10+ years of relevant industry experience. You should have knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist, exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools, and proficiency in scripting in TCL, Perl, or Python. Hands-on experience in timing/SDC constraints generation, analysis, and management is also preferred.
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