Wireless SOC Design Verification Engineer Expert
5 days ago
As a highly skilled Wireless SOC Design Verification Engineer at Apple, you will have the opportunity to work on complex SOCs. Our team integrates multiple sophisticated IP-level DV environments, crafts highly reusable best-in-class UVM Testbenches, implements effective coverage-driven and directed test cases, deploys new tools, and improves methodologies to enhance quality of tape-out readiness.
Key Responsibilities- Verify pre-silicon RTL for block and top-level SOC with comfort in all areas of SoC Design Verification engineering.
- Develop and refine verification plans from specifications, achieving targeted coverage goals.
- Architect UVM-based highly reusable test benches and integrate complex multi-instance VIPs, subsystem test benches, and test suites to SOC level.
- BS + 3 years of industry experience.
- Experience with ASIC DV, HVL methodology (UVM/OVM), and formal verification.
- Proven track record of working full ASIC cycle from concept to tape-out to bring-up, taping out large SOC systems with embedded processor cores, and verifying PCIe, Bus Fabric, NOC, AHB, AXI bus architecture in a UVM environment.
- In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, and HW/FW interaction verification.
- Knowledge of Low Power Verification.
We offer comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, reimbursement for certain educational expenses, and eligibility for discretionary bonuses or commission payments.
Estimated salary: $173,650 - $293,100 per year.
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