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Senior Advanced Design Verification Engineer

2 months ago

Santa Clara, California, United States Astera Labs Full time
Unlock the Potential of AI and Cloud Infrastructure

Astera Labs is a global leader in purpose-built connectivity solutions that empower the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable.

About the Role

As the Advanced Design Verification Engineer, you will lead next-generation ASIC infrastructure initiatives, including the development of tools and infrastructure targeting efficiency and reuse spanning DV, Emulation, pre, and post-silicon.

Key Responsibilities
  • Develop and lead next-generation ASIC infrastructure initiatives
  • Design and implement tools and infrastructure for DV, Emulation, pre, and post-silicon
  • Collaborate with cross-functional teams to drive innovation and efficiency
  • Stay up-to-date with industry trends and emerging technologies
Requirements
  • Strong academic and technical background in computer/electrical engineering
  • MS in EE or Computer Engineering preferred
  • 5+ years of related experience supporting or developing complex SoC/silicon products for Server, Storage, or Networking applications
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision
  • Entrepreneurial, open-minded behavior, and a can-do attitude
  • Authorized to work in the US and start immediately
Preferred Qualifications
  • Experience in ASIC Emulation and/or Design Verification
  • Experience with simulation and emulation platforms with domain expertise in high-speed protocols
  • Experience working with PLI/DPI and other emulation interfaces
  • Experience in programming and scripting languages (like Perl/python/C/C++)
  • Experience in a role requiring interaction with senior leadership (e.g., Director level and above)
  • Experience with high-speed protocols like PCIe/CXL
  • Experience in developing platform-agnostic transaction wrappers in C/C++ for protocols like PCIe/CXL/DDR
What We Offer

We offer a competitive salary range of $120,000.00 USD - $170,000.00 USD, determined based on your location, experience, and the pay of employees in similar positions. We are an equal opportunities employer and welcome applications from diverse backgrounds and experiences.