Verification and Validation Engineer
18 hours ago
Futran Tech Solutions Pvt. Ltd. is seeking a highly skilled Verification and Validation Engineer to join our team. As a key member of our design verification group, you will be responsible for developing testbenches in System Verilog using UVM, Python, and C.
The successful candidate will have experience in integrating C tests and APIs, creating software build flows, and setting up continuous integration and regression testing. Additionally, the role requires expertise in Unified Power Format (UPF) power-aware simulation/emulation and XProp simulation/regression TestBench creation and maintenance.
We offer a competitive salary of ₹1,200,000 per annum, along with a range of benefits including health insurance, retirement plan, and opportunities for professional growth.
Main Responsibilities:
- Testbench Development: Design and implement testbenches in UVM, Python, and C to verify digital logic circuits.
- Integration and Setup: Integrate C tests and APIs, set up continuous integration and regression testing, and develop software build flows.
- Power-Aware Simulation: Utilize Unified Power Format (UPF) for power-aware simulation/emulation.
- XProp Simulation: Create and maintain XProp simulation/regression TestBench.
- Coverage Collection: Collect and close coverage metrics.
- Documentation: Document tests, testbenches, use-cases, exclusions, and status.
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