ASIC Design Engineering Lead
19 hours ago
We are looking for a skilled ASIC Design Engineering Lead to join our team at Sql Pager LLC. As an ASIC Design Engineering Lead, you will be responsible for leading the design and verification of complex digital systems, including SoC-level and unit-level UVM verification environments.
The ideal candidate will have a strong background in designing and verifying complex digital systems, including prior experience in developing complete chip-level UVM test benches from scratch and expertise in coverage-driven System Verilog UVM with DPI-C. Proficiency in programming languages such as C/C++, Python, and/or scripting languages is also essential.
The estimated salary for this position is $180,000 - $250,000 per year, depending on experience and qualifications.
This role requires a deep understanding of bus fabrics, NoC, AMBA, and multi-CPU environments. Prior experience in verifying instruction-driven designs like CPUs and GPGPUs, knowledge of chip security, cold/warm boot sequences, and experiences using SERDES-based high-speed interfaces are preferred qualifications.
Bachelor's degree in Electrical Engineering or Computer Science is required, with a Master's degree in Science preferred.
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