Physical Design Engineer Intern

2 weeks ago


Santa Clara, California, United States Ambarella Full time
Ambarella Physical Design Intern Opportunity

We are seeking a highly motivated and detail-oriented Physical Design Intern to join our team at Ambarella. As a Physical Design Intern, you will play a critical role in supporting the physical design team with all aspects of physical design implementation and verification of our cutting-edge SoC for sub-28nm technology node.

Key Responsibilities:
  • Support the physical design team with floor-planning, auto place and route, physical implementation, timing verification, signal integrity analysis, power analysis, formal verification, and physical layout verification at block and/or full chip level.
  • Collaborate with the team to develop and implement hierarchical physical design strategies and methodologies.
  • Work with industry-leading EDA tools such as Cadence SoC Encounter, Synopsys ICC/Primetime, Magma Talus/Blast, and Mentor Calibre.
  • Develop and maintain a solid understanding of deep sub-micron technology issues and their impact on physical design.
  • Contribute to the development of project work experience using UNIX and programming languages such as C++, Perl, and TCL.
Requirements:
  • BS/MS in EE/computer science with prior internship experience in physical design.
  • Good understanding of VLSI digital design, layout, and timing closure.
  • Programming and scripting skills, including C++, Perl, and TCL.
  • Basic knowledge of circuit design, device delays, and timing at gate-level.
  • Experience with industry EDA tools and hardware design languages such as Verilog and VHDL.
  • Self-motivated team worker with good verbal and written communication skills.
  • Experience with Cadence Encounter/RTL compiler/Conformal/QRC would be an added advantage.
What We Offer:

Ambarella offers a dynamic and collaborative work environment, opportunities for professional growth and development, and a competitive compensation package.



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