Senior RTL Design Engineer
3 weeks ago
SiFive is a pioneering company that introduced RISC-V to the world, revolutionizing the future of compute by bringing the limitless potential of RISC-V to high-performance and data-intensive applications.
Our compute platforms are enabling leading technology companies to innovate, optimize, and deliver advanced solutions across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.
At SiFive, we're passionate about driving innovation and changing the world. Our success is down to our talented teams who collaborate and support each other to come up with groundbreaking ideas and solutions.
Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Job Description:Responsibilities- Architect and design new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
- Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
- Collaborate with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Work with the performance modeling team for performance exploration and optimization to meet performance goals.
- Develop and specify microarchitecture, ensuring knowledge is shared via great documentation and participation in a culture of collaborative design.
- BS/MS degree in computer science, computer engineering, electrical engineering, or related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Knowledge of at least one object-oriented and/or functional programming language.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and share the belief that engineering is teamwork.
- Knowledge of RISC-V architecture.
- Experience with Scala and/or Chisel.
- Expertise in CPU processor designs in one or more of the following areas: instruction decode, register renaming and instruction scheduling, vector units, load-store unit.
- Knowledge of verification principles, testbenches, UVM, and coverage.
SiFive provides a market-based pay structure that varies by location. The base pay range is $148,050.00-$180,950.00, and this role may be eligible for variable/incentive compensation and/or equity. In addition, this role is eligible for a comprehensive, competitive benefits package.
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
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