Senior RTL Design Engineer
3 weeks ago
SiFive is a pioneering company that introduced RISC-V to the world, revolutionizing the future of compute by bringing the limitless potential of RISC-V to high-performance and data-intensive applications.
Our compute platforms are enabling leading technology companies to innovate, optimize, and deliver advanced solutions across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.
We're passionate about connecting with talented individuals who share our enthusiasm for driving innovation and changing the world.
Our success is built on the collaboration and expertise of our talented teams, who work together to develop groundbreaking ideas and solutions that make a significant impact on people's lives.
The RoleWe're seeking a CPU Microarchitecture/RTL design engineer to join our team of passionate engineers who design industry-leading CPU cores based on the open-source RISC-V architecture.
This role involves working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Responsibilities- Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
- Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches, and tests.
- Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
- Collaborate with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Work with the performance modeling team for performance exploration and optimization to meet performance goals.
- Develop and specify microarchitecture and ensure knowledge is shared via great documentation and participation in a culture of collaborative design.
- BS/MS degree in computer science, computer engineering, electrical engineering, or related field, or equivalent experience.
- 3+ years of design experience.
- Academic or professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Strong software engineering skills, including object-oriented, aspect-oriented, and functional programming.
- Templated metaprogramming, compiler infrastructures, data modeling, and test-driven development.
- Experience with Scala/Chisel, Bluespec, or other languages/DSLs for expressing configurable hardware via software.
- Knowledge of RISC-V architecture.
- Expertise in CPU processor designs in areas such as instruction fetch, instruction decode, register renaming, and instruction scheduling.
SiFive offers a market-based pay structure, with a base pay range of $148,725.00-$181,775.00, plus variable/incentive compensation and/or equity. This role is also eligible for a comprehensive, competitive benefits package.
This position requires a successful background and reference checks, as well as satisfactory proof of your right to work in the United States of America.
SiFive is an equal opportunity employer, committed to creating an inclusive environment for all employees.
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