ASIC Design Engineer
1 month ago
Job Title: ASIC/RTL Design Engineer
Job Type: Full Time
Location: Bay Area, CA
Job Description:
We are seeking an experienced ASIC/RTL Design Engineer to join our team at Wipro. The ideal candidate will have a strong background in digital design, with expertise in System Verilog and/or Verilog RTL, and experience with high-level synthesis (HLS) and low power design.
Key Responsibilities:
- Design and integrate ASICs, including architecture and microarchitecture of System on a Chip (SoC) subsystems, Intellectual Property (IP) Functional Blocks, and sub-IPs.
- Develop and optimize digital designs using System Verilog and/or Verilog RTL, and high-level synthesis (HLS) tools.
- Collaborate with cross-functional teams to integrate and debug SoC subsystems, IPs, sub-IPs, and library components.
- Support the development and validation of IP blocks, including mapping of RTL on Zebu and HAPS.
- Design for low power and power intent design using Unified Power Format (UPF).
- Develop and optimize constraints, synthesis, timing closure, and optimization of the design.
- Perform code quality checks, including linting, clock domain crossing, and reset domain crossing.
Requirements:
- Strong background in digital design, with expertise in System Verilog and/or Verilog RTL.
- Experience with high-level synthesis (HLS) and low power design.
- Knowledge of System on a Chip (SoC) architecture and microarchitecture.
- Experience with Intellectual Property (IP) Functional Blocks and sub-IPs.
- Strong problem-solving skills and ability to work in a team environment.
What We Offer:
- Competitive salary and benefits package.
- Opportunities for professional growth and development.
- Collaborative and dynamic work environment.
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