Senior ASIC Package Design Engineer
2 weeks ago
About the Role
Socionext US is seeking a highly skilled Senior ASIC Package Design Engineer to join our team in Milpitas, CA. As a key member of our Package Design team, you will be responsible for designing and developing high-performance package substrates, ensuring signal and power integrity, and collaborating with cross-functional teams to drive product development and sales activities.
Key Responsibilities
- Design and develop high-performance package substrates, focusing on signal and power integrity analysis and routing analysis.
- Collaborate with the Director of Package Design (USA) and Package Design team in Japan to drive product development and sales activities.
- Develop and maintain a broad knowledge of package technology and design, with a deep understanding of high-performance build-up substrates, flip chip assembly, and 2.5D packaging.
- Extract and simulate package designs for signal and power integrity using tools such as HFSS and ADS.
Requirements
- Bachelor's degree in Electrical Engineering or a related field; MS preferred.
- 8-10 years of experience in semiconductor packaging design, modeling, extraction, and simulations.
- Record of success in cross-functional team environments.
- Good experience with signal and power integrity tools for package-level modeling, extraction, and simulation.
- Ability to work with Package Layout engineers.
- Strong presentation and communication skills.
Preferred Qualifications
- Hands-on experience with high-speed package and PCB design, including signal integrity and power integrity analysis, decoupling cap optimization, and characterization.
- Experience with high-speed Serdes, PCIe, LPDDR, and Ethernet interfaces, including signal integrity and power integrity analysis.
- Knowledge of packaging and PCB high-speed interconnections, including timing analysis, eye-diagram, and jitter budgeting.
- Experience with package material characterization, including frequency-dependent models, skin effects, and dielectric loss.
- Collateral packaging manufacturing and assembly rules, chip and package reliability analysis, and die-PKG-PCB PDN model time and frequency analysis.
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