Principal Verification Engineer

5 hours ago


San Jose, California, United States Rambus Full time
Overview

Rambus, a leading provider of chip and silicon IP solutions, is seeking a highly skilled Principal Verification Engineer to join our Memory Interconnect Design team in San Jose, California. As a key member of our team, you will work alongside some of the brightest inventors and engineers in the world to develop innovative products that accelerate data transfer and enhance security.

Responsibilities
  • Lead the technical verification process for full chip and/or block level designs
  • Collaborate with architects, logic, and mixed-signal designers to define verification plans
  • Implement testbenches, monitors, and scoreboards using UVM methodology
  • Achieve high code coverage goals and ensure thorough design verification
  • Work with the Lab/System team for test plan, silicon bring-up, and debug
  • Mentor junior designers and contribute to flow and methodology development
Qualifications
  • Master's degree in Electrical Engineering or related field with 10+ years of experience, or Ph.D. in Electrical Engineering with 7+ years of experience
  • Significant experience with coding in System Verilog or Verilog and UVM methodology
  • Desirable experience in verification of DDR memory interfaces
  • Strong knowledge of scripting, Linux/Unix environment, and standard ASIC verification flow/software tools
  • Excellent communication and leadership skills, with a strong commitment to working in cross-functional and globally dispersed teams
About Rambus

Rambus is a 30-year-old company that has revolutionized the semiconductor industry with its innovative products and solutions. Our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. We offer a competitive compensation package, including base salary, bonus, equity, and comprehensive benefits.



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