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Senior Principal DFT Architect

2 months ago

Boulder Creek, California, United States ARM Full time
{"h2": "Job Overview:
", "p": "At Arm, we are a leading technology company that designs and licenses semiconductor IP. Our Solutions group DFT team is responsible for implementing DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We collaborate closely with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from early investigation to tape-out and silicon test/characterization on ATE.", "ul": [{"li": "Design and architect DFT solutions for SOC catering to multiple line of business."}, {"li": "Coordinate DFT requirements across SOC, IP and product teams."}, {"li": "Implement and validate innovative DFT techniques on SOCs and sub-systems."}, {"li": "Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools."}, {"li": "Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure."}, {"li": "Participate in ATE targeted test patterns, validation and silicon-debug."}, {"li": "Work closely with Test and product engineering teams on silicon characterization and validation."}], "h2": "Required Skills and Experience:", "ul": [{"li": "Senior Principal DFT Architect with 16+ years of proven experience in Design for Test."}, {"li": "10+ years of experience handling DFT architecture for complex SOCs in leading technology nodes."}, {"li": "Core DFT skills considered crucial for this position should include some of the following: Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate level verification, silicon debug, memory and scan diagnostics."}, {"li": "Experience with 2.5D and 3D test."}, {"li": "Experience coding Verilog RTL, TCL and/or Perl."}], "h2": "Nice To Have" Skills and Experience:", "ul": [{"li": "Familiarity with SoC style architectures including multi-clock domain and low power design practices."}, {"li": "Previous experience managing a team of DFT Engineers."}, {"li": "Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug."}, {"li": "Background in design, implementation and timing convergence is a plus."}, {"li": "Experience in leading datacenter SOCs is a plus."}, {"li": "Experience with Cadence, and/or Synopsys DFT and simulation tools."}], "h2": "Salary Range:", "p": "From: $283,305
To: $383,295
", "p": "We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process."}