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Design Verification Engineer

2 months ago

Sunnyvale, California, United States Wipro Full time
Job Description

We are seeking a highly skilled Design Verification Engineer to join our team at Wipro. As a key member of our engineering team, you will be responsible for designing and developing testbenches for complex digital systems.

Key Responsibilities:
  • Testbench Development: Develop testbenches using System Verilog and Universal Methodology (UVM) to ensure thorough testing of digital systems.
  • Integration and Development: Integrate C tests and Application Programming Interfaces (APIs) with software build flow to ensure seamless testing.
  • UVM Testbench Integration: Integrate UVM testbenches to ensure comprehensive testing of digital systems.
  • Test Development and Debug: Develop and debug tests for functionality, power, performance, error, and connectivity, including tests for RTL and Gate Level Netlist Design Under Test.
  • Continuous Integration and Regression Testing: Set up and debug continuous integration and regression testing for simulation at both RTL and Gate Level Netlist.
  • Power Aware Simulation: Perform power aware simulation using Unified Power Format (UPF) to ensure efficient testing.
  • XProp Simulation and TestBench Creation: Create and maintain XProp simulation and regression testbenches.
  • Coverage Collection and Closure: Collect and close coverage to ensure thorough testing.
  • Documentation: Document tests, testbenches, use-cases, exclusions, and status to ensure transparency and accountability.
Requirements:
  • 6 to 10 years of experience in Design Verification.
  • Strong expertise in System Verilog, UVM, Python, and C.
  • Experience with integration and development of C tests and APIs.
  • Knowledge of Unified Power Format (UPF) and XProp simulation.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and documentation skills.