Synthesis Engineer

3 days ago


Austin, Texas, United States Apple Full time
Role Overview

As a Synthesis Engineer at Apple, you will play a critical role in the development of our cutting-edge chip designs. Your expertise in STA synthesis, Verilog/VHDL, and physical design concepts will enable you to optimize designs for power, area, and timing goals.

Key Responsibilities
  • Deliver timing-clean, logically equivalent netlists to the physical design team.
  • Collaborate with functional teams to question the limitations of technology and drive innovation.
  • Optimize designs for best-in-class low power and high performance using logically equivalent RTL transforms.
  • Implement ECOs and ensure timing closure.
  • Work closely with the DV team and utilize simulation and debugging tools.
Requirements
  • Bachelor's degree in Computer Science or related field.
  • 10+ years of experience in STA synthesis, Verilog/VHDL, and physical design.
  • Expertise in floor-planning, placement, congestion, and setup/hold timing closure.
  • Strong written and verbal communication skills.
  • Ability to collaborate effectively with different functional teams.
What We Offer

Apple is an equal opportunity employer committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.



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