Senior Principal Architect: On-Die Interconnect
4 days ago
We are seeking an experienced coherent interconnect architect to join our team and contribute to the development of our future AI accelerator product roadmap. This is an exciting opportunity to be at the forefront of new architecture developments in a strategically critical project.
In this role, you will work closely with our mesh architecture team to define enhancements and new sub-components for our custom interconnect IP, meeting the requirements of the product. You will be responsible for defining the topology and routing algorithms of the product for both mainband and sideband fabrics.
You will also work with, mentor, and support the architects responsible for die-to-die and chip-to-chip links to ensure that the entire interconnect network delivers the necessary performance across the system.
Key Responsibilities- Own the architecture of the product interconnect from initial path-finding to production and support it through execution to product tape-out.
- Work with the broader AI accelerator team to understand the target workloads and compute and memory needs of the product and translate this into requirements of the interconnect.
- Balance features, performance, power, and area to create a solution with high value and optimal use of development and physical resources.
- Work with the performance modeling team to evaluate critical metrics such as bandwidth and latency to ensure the interconnect is optimized for the target workloads.
- Ensure that the on-die interconnect works seamlessly with the die-to-die and chip-to-chip interfaces for efficient inter-die and inter-package communication.
- Use data-based analysis to study trade-offs that include protocol efficiency, bandwidth, and latency to inform or make critical product and IP decisions.
- Create and maintain clear, detailed, and comprehensive product architecture specs, including performance targets.
- Create and maintain configuration and programming guides as a reference for design integration and FW teams.
- Work with the existing mesh team to define and drive enhancements, additions, and other updates to our existing custom AMBA-based interconnects to meet the needs of the product.
- Help to define the cache hierarchy of the product, including any enhancements to the HW coherency protocol, to optimize the overall product based on workload analysis and by understanding the rest of the product architecture.
- Evaluate network topology and routing options to optimize for efficient data movement while ensuring the network is deadlock free.
- Define QoS, RAS, and debug requirements for the on-die interconnects.
- Drive performance correlation of models using post-silicon measurement data or pre-silicon simulation results.
- Help to define design (DV) and performance (PV) verification plans.
We are looking for a highly experienced and skilled coherent interconnect architect with a strong background in designing high-performance, high-bandwidth on-die coherent interconnects. You should have a deep understanding of cache-coherency protocols and experience with cache architecture and/or design.
Preferred qualifications include experience with chiplet-based SoC architecture, including advanced package technologies and die-to-die interface technologies and trade-offs, as well as experience with AI accelerator or GPU architectures.
You should be self-driven, curious, organized, and comfortable with ambiguity. Great communication skills are essential, as you will be working closely with the team to define and drive enhancements to our custom interconnect IP.
What We OfferAt Ampere, we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits.
The full base pay range for this role is between $163,100 and $271,900, except in the San Francisco Bay Area where the range is between $171,800 and $286,300.
We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company.
Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week.
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Santa Clara, California, United States Ampere Full timeAbout the RoleWe are seeking an experienced coherent interconnect architect to join our team and contribute to the development of our future AI accelerator product roadmap. This is an exciting opportunity to be at the forefront of new architecture developments in a strategically critical project.In this role, you will work closely with our mesh architecture...
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