ASIC Design Director
3 weeks ago
We are seeking an experienced ASIC Design Director to lead our physical design team in the development of complex high-performance networking silicon. The ideal candidate will have a strong background in physical design, including chip area estimation, chiplet partitioning, floor-planning, power estimation, synthesis, DFT, place and route, timing closure, and sign-off.
Key Responsibilities- Lead all aspects of physical design implementation, including chip area estimation, chiplet partitioning, floor-planning, power estimation, synthesis, DFT, place and route, timing closure, and sign-off.
- Build tools and improve existing infrastructure to optimize chip area and speed of execution.
- Interact with design teams to review constraints and achieve timing closure.
- Collaborate with cross-functional teams (RTL, NPI, hardware design and test, component engineering and procurement) across geographies.
- Drive physical design implementation in advanced process nodes.
- Manage a team of physical design, DFT, circuit design, and methodology development engineers.
- Develop chip execution schedules and milestone tracking.
- Communicate status and risks to senior management.
- Own power, performance, and area optimization of design.
- Develop and drive processes and automation to ensure highest efficiency and quality.
- Demonstrable management experience in leading a team that does physical design.
- Drive ASIC physical design methodology and flow from concept to release.
- Previous demonstrated experience at leading and managing large ASIC developments in advanced process nodes.
- Knowledge of industry-standard PnR and signoff tools and their capabilities.
- Understanding of the big picture and attention to detail during execution.
- Prior experience in developing physical design execution schedules.
- Knowledge and hands-on experience in block-level synthesis, place and route, timing closure.
- Understanding of advanced power analysis and power integrity analysis.
- Knowledge of scripting languages Tcl, Python.
- Manage static timing analysis, timing closure, and design constraints.
- Self-motivated, able to work in a highly cross-functional team.
- MS or Bachelor's in Electrical Engineering or Computer Science.
We offer a competitive salary range of $207,200.00 to $297,850.00 per year, as well as medical benefits, 401(k) eligibility, vacation, sick time, and parental leave. Additional details of participation in these benefit plans will be provided if an employee receives an offer of employment.
The pay range for this position is expected to be between $207,200.00 and $297,850.00/year; however, the base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience.
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