Physical Design Engineer
1 week ago
As a Physical Design Engineer on the chip implementation team at Google, you will play a key role in developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences with unparalleled performance, efficiency, and integration.
Responsibilities- Perform a dual role of static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
- Own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip timing analysis and timing ECO creation, and oversee final timing signoff for complex ASICs.
- Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
- Perform technical evaluations of EDA tools and provide recommendations, documentation, and training.
- Debug flow issues reported by your wider team and work with EDA vendors to resolve them where necessary.
- Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 8 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
- Experience with EDA tools (i.e. Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk.
- Preferred qualifications: 12 years of experience in the domain of static timing analysis.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of semiconductor device physics and, Working knowledge of SPICE simulation and complex full-chip static timing topics, including complex clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.
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