CPU Design Verification Engineer

5 days ago

Stanford, United States VMware Full time
Design Verification Engineer CPU & Server Platform

We are the CPU & Server Platform team at VMware, responsible for the ESXi operating system and core virtualization infrastructure. As a Design Verification Engineer, you will be part of our Hardware team, creating next-generation HW accelerators that significantly impact Data Center virtualization.

Key Responsibilities:
  • Build and maintain a UVM verification environment for FPGA development, at both the block and system levels, including creating behavioral models to drive and check designs consisting of RTL and third-party IP blocks.
  • Collaborate with the design team to develop test plans and analyze coverage.
  • Help build and maintain the simulation environment to efficiently run, collect results, in a timely and clear fashion.
  • Lead collaborative technical discussions to drive resolution on issues with internal teams and external HW partners.
  • Develop knowledge of system architecture, technical debug, and validation strategy.
  • Be able to work in a high-demand, fast-paced environment with lots of real-time problem-solving and critical thinking.
Requirements:
  • BS in Electrical Engineering or equivalent.
  • 5+ years of experience in ASIC/FPGA verification with UVM environments.
  • Knowledge of logic design principles, along with timing and power implications.
  • Fluency in SystemVerilog/UVM.
  • Experience in Verilog simulators and coverage tools.
  • Have developed random verification tests utilizing constrained-random, functional coverage, and assertion.
  • Familiar with standards such as networking protocol, PCIe, and memory interfaces.
  • Familiar with shell and scripting languages (Perl, Python).
  • Familiarity with SGE and similar is a plus.
  • C/C++ knowledge.
  • A great team player with a good attitude, aptitude, and can-do drive.

This role may require the candidate to comply with travel restrictions and/or work from a facility that requires full vaccination prior to entry.

Category: Engineering and Technology
Subcategory: Software Engineering
Experience: Manager and Professional
Full Time/ Part Time: Full Time
Posted Date:

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