Mixed Signal Design Verification Engineer
6 days ago
Capgemini Engineering is seeking a skilled Mixed Signal Design Verification Engineer to join our team. As a key member of our engineering team, you will be responsible for verifying and validating mixed signal designs using System Verilog and UVM.
Key Responsibilities:- Develop and execute testbenches for mixed signal designs using System Verilog
- Write regression tests for analog behavioral model verification
- Generate randomized vectors for analog behavioral model verification
- Develop checkers and write assertions for mixed signal designs
- Collaborate with cross-functional teams to ensure design verification and validation
- Proficient in System Verilog and UVM
- Experience with analog behavioral model verification
- Strong debugging skills and experience with gate-level parasitic annotated simulations
- Ability to work in a fast-paced environment and meet deadlines
Capgemini Engineering is a world leader in engineering and R&D services, combining its broad industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds. We help clients accelerate their journey towards Intelligent Industry.
With over 55,000 engineer and scientist team members in over 30 countries, Capgemini Engineering has a strong presence in various sectors, including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.
We are committed to providing a diverse and inclusive work environment, where our employees can grow and develop their skills. If you are passionate about engineering and innovation, we encourage you to apply for this exciting opportunity.
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